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1 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory flash memory pin assignment (top view) features ? thirty-two 64kb erase blocks ? deep power-down mode: 10a max ? smart 5 technology: 5v 10% v cc 5v 10% v pp application/production programming 12v v pp tolerant compatibility production programming ? address access time: 90ns ? industry-standard pinouts ? inputs and outputs are fully ttl-compatible ? automated write and erase algorithm ? two-cycle write/erase sequence options marking ? timing 90ns access -9 ? package plastic 40-pin tsop type 1 (10mm x 20mm) vg part number example: MT28F016S5VG-9 mt28f016s5 5v only, dual supply (smart 5) 40-pin tsop type i a19 a18 a17 a16 a15 a14 a13 a12 ce# v cc v pp rp# a11 a10 a9 a8 a7 a6 a5 a4 a20 nc we# oe# ry/by# dq7 dq6 dq5 dq4 v cc v ss v ss dq3 dq2 dq1 dq0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 general description the mt28f016s5 is a nonvolatile, electrically block- erasable (flash), programmable, read-only memory con- taining 2,097,152 bytes (8 bits). writing or erasing the device is done with a 5v v pp voltage, while all opera- tions are performed with a 5v v cc . due to process technology advances, 5v v pp is optimal for application and production programming. for backward compat- ibility with smartvoltage technology, 12v v pp is sup- ported for a maximum of 100 cycles and may be connected for up to 100 cumulative hours. the device is fabricated with microns advanced cmos floating- gate process. the mt28f016s5 is organized into 32 separately erasable blocks. erases may be interrupted to allow other operations with the erase suspend command. after the erase suspend command is issued, read operations may be executed. operations are executed with commands from an industry-standard command set. in addition to status register polling, the mt28f016s5 provides a ready/ busy# (ry/by#) output to indicate write and erase completion. please refer to microns web site (www.micron.com/ flash/htmls/datasheets.html) for the latest data sheet.
2 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory functional block diagram y - select gates sense amplifiers write/erase-bit compare and verify addr. buffer/ latch power (current) control addr. counter command execution logic i/o control logic v pp switch/ pump status register identification register y - decoder x - decoder/block erase control state machine a0-a20 oe# we# rp# v pp dq0-dq7 8 8 21 11 10 ce# 8 output buffer input buffer input data latch v cc ry/by# 64kb memory block (0) 64kb memory block (31) 64kb memory block (1) 64kb memory block (2) 64kb memory block (29) 64kb memory block (30) 8
3 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory pin descriptions tsop pin numbers symbol type description 38 we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is either a write to the command execution logic (cel) or to the memory array. 9 ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby power mode. 12 rp# input reset/power-down: when low, rp# clears the status register, sets the internal state machine (ism) to the array read mode and places the device in deep power-down mode. all inputs, including ce#, are dont care, and all outputs are high-z. rp# must be held at v ih during all other modes of operation. 37 oe# input output enable: enables data output buffers when low. when oe# is high, the output buffers are disabled. 24, 23, 22, 21, a0-a20 input address inputs: select a unique, 8-bit byte out of the 2,097,152 20, 19, 18, 17, available. 16, 15, 14, 13, 8, 7, 6, 5, 4, 3, 2, 1, 40 25-28, dq0-dq7 input/ data i/os: data output pins during any read operation or data input 32-35 output pins during a write. used to input commands to the cel. 36 ry/by# output ready/busy: indicates the status of the ism. when ry/by# = v ol , the ism is busy processing a command. if ry/by# = v oh , the ism is ready to accept a new command. during deep power-down, device configuration read or erase suspend, ry/by# = v oh . output is always active. 11 v pp supply write/erase supply voltage: from a write or erase confirm until completion of the operation, v pp must be at v pph (5v) (v pp ? v cc ). v pp = dont care during all other operations. 10, 31 v cc supply power supply: +5v 10%. 29, 30 v ss supply ground. 39 nc C no connect: this pin may be driven or left unconnected.
4 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory note : 1. l = v il (low), h = v ih (high), x = v il or v ih (dont care). 2. v pph = 5v. 3. ba = block address; wa = write address. 4. operation must be preceded by erase setup command. 5. operation must be preceded by write setup command. 6. the read array command must be issued before reading the array after writing or erasing. truth table 1 function rp# ce# oe# we# address v pp dq0-dq7 ry/by# standby h h xxxx high-z v oh deep power-down/reset l xxxxx high-z v oh read read h l l h x x data-out v oh output disable h l h h x x high-z v oh write/erase 2, 3 erase setup h l h l x x 20h v oh erase confirm 4 hlhlbav pph d0h v oh ? v ol write setup h l h l x x 10h/40h v oh write 5 hlhlwav pph data-in v oh ? v ol read array 6 h l h l x x ffh v oh device configuration manufacturer compatibility id h l l h 000000h x 89h v oh device id h l l h 000001h x a0h v oh
5 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory functional description the mt28f016s5 flash memory incorporates a num- ber of features that make it ideally suited for system firmware or data storage. the memory array is seg- mented into individual erase blocks. each block may be erased without affecting data stored in other blocks. these memory blocks are read, written and erased by issuing commands to the command execution logic (cel). the cel controls the operation of the internal state machine (ism), which completely controls all write, block erase and verify operations. the ism protects each memory location from over-erasure and optimizes each memory location for maximum data retention. in addition, the ism greatly simplifies the control necessary for writing the device in-system or in an external programmer. the functional description provides detailed infor- mation on the operation of the mt28f016s5 and is organized into these sections: ? overview ? memory architecture ? output (read) operations ? input operations ? command set ? ism status register ? device configuration registers ? command execution ? error handling ? write/erase cycle endurance ? power usage ? power-up overview smart 5 technology smart 5 technology allows maximum flexibility for in-system read, write and erase operations. for 5v- only systems, write and erase operations may be executed with a v pp voltage of 5v. due to process technology advances, 5v v pp is optimal for application and production programming. for backward compat- ibility with smartvoltage technology, 12v v pp is sup- ported for a maximum of 100 cycles and may be connected for up to 100 cumulative hours. however, no performance increase is realized. for any operation, v cc is at 5v. thirty-two independently erasable memory blocks the mt28f016s5 is organized into 32 indepen- dently erasable memory blocks that allow portions of the memory to be erased without affecting the rest of the memory data. internal state machine (ism) block erase and write timing are simplified with an ism that controls all erase and write algorithms in the memory array. the ism ensures protection against over-erasure and optimizes write margin to each cell. during write operations, the ism automatically increments and monitors write attempts, verifies write margin on each memory cell and updates the ism status register. when a block erase is performed, the ism automatically overwrites the entire addressed block (eliminates overerasure), increments and monitors erase attempts, and sets bits in the ism status register. ism status register the ism status register allows an external processor to monitor the status of the ism during write and erase operations. two bits of the 8-bit status register are set and cleared entirely by the ism. these two bits indicate whether the ism is busy with an erase or write task and when an erase has been suspended. additional error information is set in three other bits: v pp status, erase status and write status. these three bits must be cleared by the host system. ready/busy# (ry/by#) output in addition to status register polling, the mt28f016s5 provides an asynchronous ry/by# output to indicate the status of the ism. ry/by# is v oh when the state machine is inactive and v ol during a write or erase operation. this output is always active. command execution logic (cel) the cel receives and interprets commands to the device. these commands control the operation of the ism and the read path (i.e., memory array, device configuration or status register). commands may be issued to the cel while the ism is active. however, there are restrictions on what commands are allowed in this condition. see the command execution section for more detail. deep power-down mode to allow for maximum power conservation, the mt28f016s5 features a very low current, deep power- down mode. to enter this mode, the rp# pin is taken to v ss 0.2v. in this mode, the current draw is a maximum of 10a. entering deep power-down also clears the status register and sets the ism to the read array mode.
6 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory memory architecture the mt28f016s5 memory array architecture is de- signed to allow sectors to be erased without disturbing the rest of the array. the array is divided into 32 addressable blocks that are independently erasable. when blocks rather than the entire array are erased, the total device endurance is enhanced, as is system flex- ibility. only the erase functions are block-oriented. all read and write operations are done on a random- access basis. figure 1 illustrates the memory address map. output (read) operations the mt28f016s5 features three different types of reads. depending on the current mode of the device, a read operation will produce data from the memory array, status register or one of the device configuration registers. in each of these three cases, the we#, ce# and oe# inputs are controlled in a similar manner. moving between modes to perform a specific read will be covered in the command execution section. memory array to read the memory array, we# must be high, and oe# and ce# must be low. valid data will be output on the dq pins once these conditions have been met and a valid address is given. valid data will remain on the dq pins until the address changes, or until oe# or ce# goes high, whichever occurs first. the dq pins will continue to output new data after each address transition as long as oe# and ce# remain low. after power-up or reset, the device will automati- cally be in the array read mode. all commands and their operations are covered in the command set and com- mand execution sections. status register performing a read of the status register requires the same input sequencing as a read of the array except that the address inputs are dont care. data from the status register is latched on the falling edge of oe# or ce#, whichever occurs last. if the contents of the status register change during a read of the status register, either oe# or ce# may be toggled while the other is held low to update the output. following a write or erase operation, the device automatically enters the status register read mode. in addition, a read during a write or erase operation will produce the status register contents on dq0-dq7. when the device is in erase suspend mode, a read operation will produce the status register contents until another command is issued. while the device is in certain other modes, read status register may be given to return to the status register read mode. all commands and their operations are covered in the command set and command execution sections. device configuration registers reading any of the device configuration registers requires the same input sequencing as reading the status register except that specific addresses must be issued. we# must be high, and oe# and ce# must be low. to read the manufacturer compatibility id, ad- dresses must be at 000000h, and to read the device id, addresses must be at 000001h. while the device is in certain other modes, read device configuration may be given to return to the configuration registers read mode. all commands and their operations are covered in the command set and command execution sections. figure 1 memory address map 31 0 64kb 16mb 64kb 64kb
7 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory input operations the dq pins are used either to input data to the array or to input a command to the cel. a command input issues an 8-bit command to the cel to control the mode of operation of the device. a write is used to input data to the memory array. the following section describes both types of inputs. more information de- scribing how to use the two types of inputs to write or erase the device is provided in the command execution section. commands to perform a command input, oe# must be high, and ce# and we# must be low. addresses are dont care but must be held stable, except during an erase confirm. the 8-bit command is input on dq0-dq7 and is latched on the rising edge of ce# (ce#-con- trolled) or we# (we#-controlled), whichever occurs first. memory array a write to the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. setting any bits to a logic 1 requires that the entire block be erased. to perform a write, oe# must be high, ce# and we# must be low, and v pp must be set to v pph (5v). a0-a20 provide the address to be written, while the data to be written to the array is input on the dq pins. the data and addresses are latched on the rising edge of either ce# (ce#-controlled) or we# (we#-controlled), whichever occurs first. a write must be preceded by a write setup command. details on how to input data to the array will be covered in the write sequence section. command set to simplify writing of the memory blocks, the mt28f016s5 incorporates an ism that controls all internal algorithms for the write and erase cycles. an 8-bit command set is used to control the device. details on how to sequence commands are provided in the command execution section. table 1 lists the valid commands. ism status register the 8-bit ism status register (see table 2) is polled to check for write or erase completion or any related errors. during or following a write, erase or erase suspend, a read operation will output the status register contents on dq0-dq7 without prior com- mand. while the status register contents are read, the outputs will not be updated if there is a change in the ism status unless oe# or ce# is toggled. if the device is not in the write, erase, erase suspend, status register or read mode, read status register (70h) can be issued to view the status register contents. all of the defined bits are set by the ism, but only the ism and erase suspend status bits are reset by the ism. the erase, write and v pp status bits must be cleared using clear status register (50h). this allows the user to choose when to poll and clear the status register. for example, the host system may perform multiple write operations before checking the status register instead of checking after each individual write. as- serting the rp# signal or powering down the device will also clear the status register. device configuration registers the device id and manufacturer compatibility id can be read by issuing read device configura- tion (90h). to read the desired register, a specific address must be asserted. see table 3 for more details on the various device configuration registers.
8 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory table 1 command set command hex code description reserved 00h this command and all unlisted commands are invalid and should not be called. these commands are reserved to allow for future feature enhancements. read array ffh must be issued after any other command cycle before the array can be read. it is not necessary to issue this command after power-up or reset. read device configuration 90h allows the device id and manufacturer id to be read. please refer to table 3 for more information on the various device configuration registers. read status register 70h allows the status register to be read. please refer to table 2 for more information on the status register bits. clear status register 50h clears status register bits 3-5, which cannot be cleared by the ism. erase setup 20h the first command given in the two-cycle erase sequence. the erase will not be completed unless followed by erase confirm. erase confirm d0h the second command given in the two-cycle erase se- quence. must follow an erase setup to be valid. also used during a write/erase suspend to resume the write or erase. write setup 40h or the first command given in the two-cycle write sequence. 10h the write data and address are given in the following cycle to complete the write. erase suspend b0h requests a halt of the erase and puts the device into the erase suspend mode. when the device is in this mode, only read status register, read array and erase confirm (erase resume) commands may be executed.
9 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory table 2 status register status bit # status register bit description sr7 ism status the isms bit displays the active status of the state machine 1 = ready during write or block erase operations. the controlling 0 = busy logic polls this bit to determine when the erase and write status bits are valid. sr6 erase suspend status issuing an erase suspend places the ism in the suspend 1 = erase suspended mode and sets this and the isms bit to 1. the ess bit will 0 = erase in progress/completed remain 1 until an erase confirm is issued. sr5 erase status es is set to 1 after the maximum number of erase cycles is 1 = block erase error executed by the ism without a successful verify. es is only 0 = successful block erase cleared by a clear status register command or by a reset. sr4 write status ws is set to 1 after the maximum number of write cycles 1 = write error is executed by the ism without a successful verify. ws is only 0 = successful write cleared by a clear status register command or by a reset. sr3 v pp status v pp s detects the presence of a v pp voltage. it does not 1 = no v pp voltage detected monitor v pp continuously, nor does it indicate a valid v pp 0 = v pp present voltage. the v pp pin is sampled for 5v after write or erase confirm is given. v pp s must be cleared by clear status register or by a reset. sr0-2 reserved reserved for future use. table 3 device configuration device configuration address data condition manufacturer compatibility id 000000h 89h manufacturer compatibility id read device id 000001h a0h device id read
10 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory table 4 command sequences bus 1st 2nd cycles cycle cycle commands reqd operation address data operation address data notes read array 1 write x ffh 1 read device configuration 2 write x 90h read ca cd 2, 3 read status register 2 write x 70h read x srd 4 clear status register 1 write x 50h erase setup/confirm 2 write x 20h write ba d0h 5, 6 erase suspend/resume 2 write x b0h write x d0h write setup/write 2 write x 40h write wa wd 6, 7 alternate write 2 write x 10h write wa wd 6, 7 command execution commands are issued to bring the device into different operational modes. each mode allows specific operations to be performed. several modes require a sequence of commands to be written before they are reached. the following section describes the properties of each mode, and table 4 lists all command sequences required to perform the desired operation. read array the array read mode is the initial state of the device upon power-up and is also entered after a reset. if the device is in any other mode, read array (ffh) must be given to return to the array read mode. unlike the write setup command (40h), read array does not need to be given before each individual read access. device configuration to read the device id and manufacturer compatibil- ity id, the read device configuration (90h) command must be issued. while the device is in this mode, specific addresses must be issued to read the desired information. the manufacturer compatibility id is read at 000000h, and the device id is read at 000001h. write sequence two consecutive cycles are needed to input data to the array. write setup (40h or 10h) is given in the first cycle. the next cycle is the write, during which the write address and data are issued and v pp is brought to v pph . the ism will now begin to write the byte. v pp must be held at v pph until the write is completed (sr7 = 1 and ry/by# = v oh ). while the ism executes the write, the ism status bit (sr7) will be at 0 and ry/by# = v ol , and the device will not respond to any commands. any read opera- tion will produce the status register contents on dq0- dq7. when the ism status bit (sr7) is set to a logic 1 and ry/by# = v oh , the write has been completed, and the device will go into the status register read mode until another command is given. note: 1. must follow write or erase confirm commands to the cel in order to enable flash array read cycles. 2. ca = configuration address: 00000h for manufacturer compatibility id and 00001h for device id. 3. cd = configuration data. 4. srd = status register data. 5. ba = block address. 6. addresses are dont care in first cycle but must be held stable. 7. wa = address to be written; wd = data to be written to wa.
11 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory erase sequence executing an erase sequence will set all bits within a block to logic 1. the command sequence necessary to execute an erase is similar to that of a write. to provide added security against accidental block era- sure, two consecutive command cycles are required to initiate an erase of a block. in the first cycle, addresses are dont care, and erase setup (20h) is given. in the second cycle, v pp is brought to v pph , an address within the block to be erased is issued, and erase confirm (d0h) is given. if a command other than erase confirm is given, the write and erase status bits (sr4 and sr5) will be set, and the device will be in the read status mode. after the erase confirm (d0h) is issued, the ism will start the erase of the addressed block. any read operation will output the status register contents on dq0-dq7. v pp must be held at v pph until the erase is completed (sr7 = 1 and ry/by# = v oh ). once the erase is completed, the device will be in the status register read mode until another command is issued. erase suspension the only command that may be issued while an erase is in progress is erase suspend. this command allows other commands to be executed while pausing the erase in progress. once the device has reached the suspend mode, the erase suspend status bit (sr6) and ism status bit (sr7) will be set and ry/by# will transi- tion to v oh . the device may now be given a read array, erase resume or read status register command. after read array has been issued, any location not within the block being erased may be read. if erase resume is issued before sr6 has been set, the device will immediately proceed with the erase in progress. during an erase suspend, v pp and rp# must remain at the same levels used for the erase. error handling after the ism status bit (sr7) has been set, v pp (sr3), write (sr4) and erase (sr5) status bits may be checked. if one or a combination of these four bits has been set, an error has occurred. the ism cannot reset these four bits. to clear these bits, clear status register (50h) must be given. table 6 lists the combination of errors. write/erase cycle endurance the mt28f016s5 is designed and fabricated to meet advanced firmware and data storage requirements. to ensure this level of reliability, v pp must be at 5v 10% during write or erase cycles. for smartvoltage- compatible production programming, 12v v pp is sup- ported for a maximum of 100 cycles and may be connected for up to 100 cumulative hours. operation outside these limits may reduce the number of write and erase cycles that can be performed on the device. power usage the mt28f016s5 offers several power-saving fea- tures that may be utilized in the array read mode to conserve power. deep power-down mode is enabled by bringing rp# to v ss 0.2v. current draw (i cc ) in this mode is a maximum of 10a. when ce# is high, the device will enter standby mode. in this mode, maxi- mum i cc current is 100a. if ce# is brought high during a write or erase, the ism will continue to operate, and the device will consume the respective active power until the write or erase is completed. power-up the likelihood of unwanted write or erase opera- tions is minimized since two consecutive cycles are required to execute either operation. however, to reset the ism and to provide additional protection while v cc is ramping, one of the following conditions must be met: ? rp# must be held low until v cc is at valid func- tional level; or ? ce# or we# may be held high and rp# must be toggled from v cc -gnd-v cc . after a power-up or reset, the status register is reset, and the device will enter the array read mode. figure 2 power-up/reset timing diagram valid valid v cc (5v) data address undefined t note 1 rp# rwh t aa note: 1. v cc must be within the valid operating range before rp# g oes high.
12 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory table 6 status register error decode 1 status bits sr5 sr4 sr3 error description 2 0 0 0 no errors 001v pp voltage error 0 1 0 write error 0 1 1 write error, v pp voltage not valid 1 0 0 erase error 1 0 1 erase error, v pp voltage not valid 1 1 0 command sequencing error note: 1. sr3-sr5 must be cleared using clear status register. 2. sr3-sr4 reflect noncumulative results.
13 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory complete write status-check sequence self-timed write sequence 1 yes no write 40h or 10h v pp = 5v v pp v cc start write byte address/data status register read sr7 = 1? complete status check (optional) write complete 3 2 no start (write completed) yes sr4 = 0? sr3 = 0? no yes write error 5 write successful v pp error 4, 5 note: 1. sequence may be repeated for additional writes. 2. complete status check is not required. 3. device will be in status register read mode. to return to the array read mode, the ffh command must be issued. 4. if sr3 is set during a write or block erase attempt, clear status register (50h) should be issued before further write or erase operations are attempted. 5. status register bits 3-5 must be cleared using clear status register.
14 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory yes no v pp = 5v v pp v cc complete status check (optional) erase complete no yes suspend erase? status register or ry/by# polling sr7 = 1? write 20h start write d0h, block address suspend sequence erase resumed erase busy 3 4 2 self-timed block erase sequence 1 complete block erase status-check sequence no start (block erase completed) yes sr4, 5 = 1? sr3 = 0? yes yes command sequence error sr5 = 0? no 6 6 v error pp block erase 5, 6 erase successful note: 1. sequence may be repeated to erase additional blocks. 2. complete status check is not required. 3. to return to the array read mode, the ffh command must be issued. 4. refer to the erase suspend flowchart for more information. 5. if sr3 is set during a write or block erase attempt, clear status register (50h) should be issued before further write or erase operations are attempted. 6. status register bits 3-5 must be cleared using clear status register.
15 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory erase suspend sequence no write b0h (erase suspend) start (erase in progress) write ffh (read array) status register read yes sr6 = 1? sr7 = 1? no yes no yes done reading? write d0h (erase resume) resume erase erase completed v pp = 5v v pp v cc
16 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory electrical characteristics and recommended dc read operating conditions (0c t a +70c) parameter/condition symbol min max units notes 5v supply voltage v cc 4.5 5.5 v 1 input high (logic 1) voltage, all inputs v ih 2v cc + 0.5 v 1 input low (logic 0) voltage, all inputs v il -0.5 0.8 v 1 absolute maximum ratings* voltage on v cc supply relative to v ss ............................. -0.5v to +6v** input voltage relative to v ss ................ -0.5v to +6v** v pp voltage relative to v ss ................. -0.5v to +12.6v ? temperature under bias ...................... -10c to +80c storage temperature (plastic) ............ -55c to +125c power dissipation ................................................... 1w *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **v cc , input and i/o pins may transition to -2v for <20ns and v cc + 2v for <20ns. ? voltage may pulse to -2v for <20ns and 14v for <20ns. dc operating characteristics (0c t a +70c) parameter/condition symbol min max units notes output voltage levels (ttl) v oh 1 2.4 C v output high voltage (i oh = -2.5ma) 1 output low voltage (i ol = 5.8ma) v ol C 0.45 v output voltage levels (cmos) v oh 2 v cc - 0.4 C v 1 output high voltage (i oh = -100a) input leakage current any input (0v v in v cc ); i l -1 1 a all other pins not under test = 0v output leakage current i oz -10 10 a (d out is disabled; 0v v out v cc ) note: 1. all voltages referenced to v ss .
17 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory capacitance (t a = +25c; f = 1 mhz) parameter/condition symbol max units notes input capacitance c i 8pf output capacitance c o 12 pf read and standby current drain (0c t a +70c; v cc = +5v 10%) parameter/condition symbol typ max units notes read current: ttl input levels i cc 1 8 50 ma 1, 2 (ce# = v il ; oe# = v ih ; f = 8 mhz; other inputs = v il or v ih ; rp# = v ih ) read current: cmos input levels (ce# 0.2v; oe# ? v cc - 0.2v; f = 8 mhz; other inputs 0.2v i cc 2 5 35 ma 1, 2 or ? v cc - 0.2v; rp# = v cc - 0.2v) standby current: ttl input levels v cc power supply standby current i cc 3 0.2 2 ma (ce# = rp# = v ih ; other inputs = v il or v ih ) standby current: cmos input levels v cc power supply standby current i cc 4 65 100 a (ce# = rp# = v cc - 0.2v) deep power-down current: v cc supply (rp# = v ss 0.2v) i cc 5 120a standby or read current: v pp supply (v pp ? v cc )i pp 1 2 15 a deep power-down current: v pp supply (rp# = v ss 0.2v) i pp 2 25a note: 1. i cc is dependent on cycle rates. 2. i cc is dependent on output loading. specified values are obtained with the outputs open.
18 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory read timing parameters electrical characteristics and recommended ac operating conditions (0c t a +70c; v cc = +5v 10%) ac characteristics -9 parameter symbol min max units notes read cycle time t rc 90 ns access time from ce# t ace 90 ns 1 access time from oe# t aoe 45 ns 1 access time from address t aa 90 ns rp# high to output valid delay t rwh 400 ns oe# or ce# high to output in high-z t od 20 ns output hold time from oe#, ce# or address change t oh 0 ns ac test conditions input pulse levels ............................................... 0.4v to 2.4v input rise and fall times ................................................ <10ns input timing reference level .............................. 0.8v and 2v output timing reference level ........................... 0.8v and 2v output load ................................. 1 ttl gate and c l = 100pf note: 1. oe# may be delayed by t ace minus t aoe after ce# falls before t ace is affected.
19 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory timing parameters -9 symbol min max units t rc 90 ns t ace 90 ns t aoe 45 ns t aa 90 ns read cycle valid data valid address ce# a0-a20 oe# dq0-dq7 t rc t ace t aoe t od t oh t aa we# rp# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t rwh don? care undefined -9 symbol min max units t rwh 400 ns t od 20 ns t oh 0 ns
20 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory write/erase current drain (0c t a +70c; v cc = +5v 10%; v pp = +5v 10% [note 2]) parameter/condition symbol max units notes write current: v cc supply i cc 6 35 ma 3 write current: v pp supply i pp 3 40 ma 3 erase current: v cc supply i cc 7 30 ma 3 erase current: v pp supply i pp 4 20 ma 3 erase suspend current: v cc supply i cc 8 10 ma 3, 4 (erase suspended) erase suspend current: v pp supply i pp 5 200 a (erase suspended) recommended dc write/erase conditions (0c t a +70c; v cc = +5v 10%) parameter/condition symbol min max units notes v pp write/erase lockout voltage v pplk C 1.5 v 1 v pp voltage during write/erase operation v pph 4.5 5.5 v 2 v cc write/erase lockout voltage v lko 2Cv note: 1. absolute write/erase protection when v pp v pplk . 2. for smartvoltage-compatible production programming, 12v v pp is supported for a maximum of 100 cycles and may be connected for up to 100 cumulative hours. 3. sampled, not tested, 100%. 4. parameter is specified when device is not accessed. actual current draw will be i cc 8 (5v v cc ) plus current of operation being executed while the device is in suspend mode.
21 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory write and erase duration characteristics 5v v pp parameter typ max units notes write time 8 tbd s 1 block erase time 0.5 tbd s 1 block write time 0.5 tbd s 1, 2, 3 erase suspend latency to read 9 12 s 1 speed-dependent write/erase ac timing characteristics and recommended ac operating conditions: we# (ce#)-controlled writes (0c t a +70c; v cc = +5v 10%) ac characteristics -9 parameter symbol min units notes write cycle time t wc 90 ns we# (ce#) high pulse width t wph ( t cph) 25 ns we# (ce#) pulse width t wp ( t cp) 50 ns address setup time to we# (ce#) high t as 40 ns address hold time from we# (ce#) high t ah 5 ns data setup time to we# (ce#) high t ds 40 ns data hold time from we# (ce#) high t dh 5 ns ce# (we#) setup time to we# (ce#) low t cs ( t ws) 0 ns ce# (we#) hold time from we# (ce#) high t ch ( t wh) 0 ns v pp setup time to we# (ce#) high t vps 100 ns rp# high to we# (ce#) low delay t rs 1,000 ns write duration t wed1 6 s block erase duration t wed2 600 ms write recovery to read t wr 0 ns v pp hold time from status data valid, ry/by# high t vph 0 ns we# (ce#) high to ry/by# low t ryby 90 ns we# (ce#) high to busy status (sr7 = 0) t wb 200 ns note: 1. typical values measured at t a = +25c. 2. assumes no system overhead. 3. typical write times use checkerboard data pattern.
22 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory write/erase cycle we#-controlled write/erase ce# a0-a20 oe# dq0-dq7 t wc t wed1, 2 we# rp# v ih v il t rs a in v pp v ih v il t ch t cs v pph1 v pph2 t as t ah t wp t wph t ds t dh cmd in cmd/ data-in cmd in write setup or erase setup input write or erase executed, status register checked for completion command for next operation issued t dh t ds write or block address asserted, and write data or erase confirm v ih v il v ih v il v ih v il v ih v il t wr note 1 t as t ah v il ry/by# t wb t ryby v oh v ol v hh t vps t vph [5v v pp ] [12v v pp ] status (sr7=1) status (sr7=0) dont care t vps 2 100 ns t rs 1,000 ns t vph 2 0ns t ryby 90 ns t wb 200 ns t wed1 6 s t wed2 600 ms t wr 0 ns timing parameters -9 symbol min units t wc 90 ns t wph 25 ns t wp 50 ns t as 40 ns t ah 5 ns t ds 40 ns t dh 5 ns t cs 0 ns t ch 0 ns -9 symbol min units note: 1. address inputs are dont care but must be held stable. 2. measured with v pp = v pph = 5v.
23 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory write/erase cycle ce#-controlled write/erase note: 1. address inputs are dont care but must be held stable. 2. measured with v pp = v pph = 5v. t vps 2 100 ns t rs 1,000 ns t vph 2 0ns t ryby 90 ns t wb 90 ns t wed1 6 s t wed2 600 ms t wr 0 ns timing parameters -9 symbol min units t wc 90 ns t cph 25 ns t cp 50 ns t as 40 ns t ah 5 ns t ds 40 ns t dh 5 ns t ws 0 ns t wh 0 ns -9 symbol min units dont care we# a0-a20 oe# dq0-dq7 t wc t wed1, 2 ce# rp# v ih v il t rs a in v pp v ih v il t wh t ws v pph1 v pph2 t as t ah t cp t cph t ds t dh cmd in cmd/ data-in cmd in write setup or erase setup input write or erase executed, status register checked for completion command for next operation issued t dh t ds write or block address asserted, and write data or erase confirm v ih v il v ih v il v ih v il v ih v il t wr t vps note 1 t as t ah v il ry/by# t wb t ryby v oh v ol v hh status (sr7=1) status (sr7=0) t vph [5v v pp ] [12v v pp ]
24 2 meg x 8 smart 5 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. f42.p65 C rev. 1/00 ?2000, micron technology, inc. advance 2 meg x 8 smart 5 even-sectored flash memory 40-pin plastic tsop i (10mm x 20mm) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01 per side. detail a .721 (18.31) .780 (19.81) .397 (10.08) .010 (0.25) .0197 (0.50) .010 (0.25) .007 (0.18) see detail a .795 (20.19) .727 (18.47) .006 (0.15) typ .005 (0.13) .391 (9.93) .024 (0.60) .016 (0.40) .008 (0.20) .004 (0.10) .002 (0.05) .0315 (0.80) .047 (1.20) max 40 1 20 21 .010 (0.25) plane gage pin #1 index 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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